1. Field of the Invention
The present invention relates to a semiconductor device, such as a semiconductor memory or the like, and to a semiconductor device which has redundant memory cell arrays and serially accesses addresses.
2. Description of the Related Art
A semiconductor device of this type has heretofore been used for the sake of judging whether or not an address specified by a pair of address signals serially supplied from the outside corresponds to any of addresses of defective memory cells. As a result of judgement, when a defective memory cell exists in a memory cell array, the defective memory cell is replaced by a corresponding redundant memory cell for writing data therein and reading it therefrom. A memory selective unit of this type of semiconductor device has a redundant memory selective circuit, a serial/parallel conversion circuit, and a counter. The redundant memory selective circuit outputs a memory selective signal MS for bringing the memory cell array and each of the redundant memory cell arrays to operating and non-operating states respectively. When the specified address is found to be an address of a normal memory cell, the redundant memory selective circuit brings the memory selective signal to a high level. When the specified address is found to be the address of the defective memory cell, the redundant memory selective circuit brings the memory selective signal to a low level. Thus, the defective memory cell can be relieved by being replaced with the redundant memory cell array.
The serial/parallel conversion circuit converts the serial address signals to parallel address signals respectively. Thereafter, the redundant memory selective circuit judges whether or not the specified address corresponds to the address of the defective memory cell. In this case, the redundant memory selective circuit outputs a memory selective signal therefrom. When the specified address is of the address of the normal memory cell, the memory selective signal is brought to the high level. On the other hand, when the specified address is of the address of the defective memory cell, the memory selective signal is brought to the low level.
When the defective memory cell is specified by the memory selective signal, it is replaced by the redundant memory cell array. This replacement is performed after the elapse of one cycle from the completion of each serial address. This means that the writing of data to and reading of the same from the memory cell array must also wait for decision made by the memory selective signal, so as to be performed after one cycle or later from the completion of each serial address.
Namely, since the redundant memory selective circuit in the conventional semiconductor device is not supplied with those other than the external addresses in its structure after it has been reset by a precharge signal, it is necessary to provide a flip-flop for latching only the parallel-converted external addresses at a final stage of the serial/parallel conversion circuit and set a cycle in which the flip-flop latches the addresses. Therefore, the determination of the memory selective signal is performed after one cycle since the completion of the serial addresses. Thus, the conventional semiconductor device has a drawback in that the writing and reading of data into and from the memory cell array are also performed after this cycle, thus resulting in interference with the speeding up of a memory access.
Further, the semiconductor device has a drawback in that when the external addresses have specified the address of the defective memory cell, the redundant memory selective circuit requires time to bring the memory selective signal to the low level and hence this interferes with the speeding up of the memory access even from this point of view.
Moreover, the semiconductor device has a drawback in that loads on COMP (complementary) signals become heavy which include the capacities of diffused layers of transistors provided by the same number as the number of bits of addresses and the capacities of fuses or the like. Even when each external address differs from the address of the defective memory cell only by a single bit, the memory selective signal must be put into a low level under a heavy load situation of the transistors.